1. Field of the Invention
The present invention relates to a compound semiconductor field-effect transistor.
2. Description of the Related Art
HEMTs (High Electron Mobility Transistors) which are compound semiconductor field-effect transistors with a heterojunction are widely used as a high-frequency microwave device because their electron mobility is high and operating speed is fast. The HEMTs are also expected to be applied to digital ICs for their high-speed operation.
Conventional compound semiconductor field-effect transistors suffer traps (deep levels due to impurity atoms and crystalline defects) such as substrate traps present in the semiconductor substrate and a number of interfacial traps present in the interface between the semi-insulating substrate and an epitaxial growth layer, and hence are subject to variations in the transistor current, which pose a serious problem in their applications.
Solutions to such a problem include using a p-type substrate in place of the semi-insulating substrate and inserting a p-type layer below a channel layer to electrically insulate the channel layer from the traps. However, if the p-type layer is inserted in a shallow position or a p-type substrate of high concentration is used, then a drain parasitic capacitance between a drain electrode and the p-type layer tends to increase, or the inserted p-type layer greatly lowers a drain saturated current due to its substrate effect. These schemes cannot be employed because they impair the high-speed performance of the transistors. If the p-type layer is inserted in a deep position or a p-type substrate of low concentration is used, then the shield effect of the p-type layer is reduced in a region where the electron concentration is low, and the electron concentration in the channel is varied owing to a change in the charge of the traps, resulting in a variation in the drain current. Furthermore, these solutions are unable to suppress a short channel effect that increases the drain conductance which is caused when the channel length is reduced.
According to a conventional field-effect transistor, e.g., a silicon MOSFET, in order not to lower the operating speed of the transistor, a p-type layer is inserted into a relatively deep region which has a depth that is about three times the thickness of the oxide film though the short channel effect cannot effectively be suppressed. In view of the ratio of about 3:1 between the dielectric constant of the compound semiconductor and the dielectric constant of the oxide film, the above depth corresponds to a depth that is about nine times the thickness of an electron supply layer of AlGaAs for the compound transistor HEMT. Since the AlGaAs layer is about 30 nm thick, the optimum depth of the p-type layer in the compound transistor HEMT, as estimated from the silicon MOSFET technology, is about 270 nm.
An example of compound transistor where the p-type layer is inserted in a relatively deep position is described in an article entitled "Shielding Effects of a Drain Lag Phenomena by a p-Buffer Layer", p. 101, written by Nogome, Kunihiro, Ohno, in collected lecture papers, Electronics 2, of the general conference of the Electronics Information Communications Society, 1996. According to the process described in the article, a p-type layer is placed at a depth which is about 200 nm from the channel layer, and a p-type ohmic electrode is connected to one end of the p-type layer for fixing a potential to shield traps and reduce their influences. In the compound semiconductor with the p-type layer inserted at the depth which is about 200 nm from the channel layer, however, as indicated by the article, a tradeoff occurs between the trap shield effect and an increased parasitic capacitance, failing to provide semiconductor devices of desired good characteristics.
FIG. 1 of the accompanying drawings shows in cross section a conventional compound semiconductor field-effect transistor.
As shown in FIG. 1, the conventional compound semiconductor field-effect transistor comprises a semi-insulating substrate 1, a buffer layer 10 disposed on the semi-insulating substrate 1, a p-type layer 9 disposed on the buffer layer 10, an undoped GaAs layer 8 disposed on the p-type layer 9 and having an upper portion which will act as a channel layer 8a where electrons pass when a voltage is applied, an electron supply layer 7 disposed on the undoped GaAs layer 8 for supplying electrons to the channel layer 8a, two etching stop n-type layers 6 disposed on the electron supply layer 7 for use in selective etching, two ohmic electrode cap n-type layers 5 disposed respectively on the etching stop n-type layers 6, a source electrode 2 disposed on one of the ohmic electrode cap n-type layers 5, a gate electrode 3 disposed on the electron supply layer 7, and a drain electrode 4 disposed on the other ohmic electrode cap n-type layer 5. The channel layer 8a comprises a surface layer of the undoped GaAs layer 8, and does not have an appreciable thickness as compared with the other layers. An interfacial trap 11 is developed between the semi-insulating substrate 1 and the buffer layer 10.
In the conventional compound semiconductor field-effect transistor, the p-type layer 9 is inserted in a position at a depth that is greater than three times the distance between the gate electrode 3 and the channel layer 8a in order to suppress the substrate effect and the drain parasitic capacitance.
Because the p-type layer for preventing the influences of traps including the substrate trap and the interfacial trap is inserted in a deep position to avoid the substrate effect and the drain parasitic capacitance, the conventional compound semiconductor field-effect transistor has been subject to the following difficulties:
(1) The drain conductance increases due to the short channel effect. PA1 (2) The electric shield effect between the channel layer and the traps is reduced, varying the drain current.